1. Field of the Invention
This invention generally relates to semiconductor device fabrication, and more particularly to a method for making a metal-insulator-metal capacitor having a damascene structure which may be used, for example, in back end of the line (BEOL) integrated circuits.
2. Description of the Related Art
Various capacitive structures are used in integrated circuits. These structures include metal-oxide-semiconductor (MOS) capacitors, p-n junction capacitors, and metal-insulator-metal (MIM) capacitors. For some applications, MIM capacitors provide certain advantages over MOS and p-n junction capacitors because the frequency characteristics of MOS and p-n junction capacitors are restricted as a result of depletion layers that form in the semiconductor electrodes. MIM capacitors, on the other hand, are preferential because they exhibit improved frequency and temperature characteristics. Also, MIM capacitors are formed in the metal interconnect layers which reduce CMOS transistor process integration interactions or complications. Additionally, the topology of a MIM capacitor simplifies planarization processes.
In spite of their advantages, conventional methods for making metal-insulator-metal (MIM) capacitors are undesirable in a number of respects. For example, conventional methods perform multiple masking, etching, and polishing steps in order to form the capacitor plates and dielectric. This typically involves performing three masking steps to form the plates and dielectric elements of the capacitor. This is accompanied by three separate reactive ion etching steps, each of which is followed by a cleaning step to prevent contamination. These steps, when repetitively performed, increase the time, cost, and complexity of the manufacturing process.
In order to electrically connect the capacitor to other elements of the circuit, it is clear that some form of wiring must be formed near the capacitor. Conventional methods usually form this wiring after the capacitor has been formed. The use of separate process steps to form this wiring has also proven adverse to process efficiency.
Moreover, this wiring is conventionally located on a level of the device different from the capacitor level. This adversely impacts the integration density of the device.
Structurally speaking, MIM capacitors have traditionally used aluminum as the metal for their conductive plates. This use of aluminum has proven to be undesirable for a number of reasons, not the least of which include the high sheet resistance and surface roughness that results from the use of this metal. Both of these effects adversely impacts device performance and thus are highly undesirable.
Efforts have been made to use more favorable materials in integrated circuit design. Most recently, copper has been used to form interconnects structures for multi-layer semiconductor devices. U.S. Pat. No. 6,117,747 discloses one such technique where the upper and lower plates of a metal-oxide-metal capacitor are connected to other circuit elements using dual damascene copper interconnects and metal lines. In spite of the use of copper, this device is still undesirable because the aluminum is used to form the capacitor plates and thus this device has all of the previously mentioned drawbacks associated with the use of this metal. Furthermore, using aluminum in a copper interconnect integration scheme substantially increases the overall time of manufacture because additional process steps of deposition, patterning and etching are required. U.S. Patent Nos. 6,174,812 and 6,174,804 also disclose methods for forming copper interconnects in integrated circuit devices.
In view of the foregoing, it is cleat that a need exists for a method of making a MIM capacitor which uses fewer process steps than conventional methods, thereby improving manufacturing efficiency in terms of time, cost, and complexity. There is also a need for a MIM capacitor which is formed from materials that demonstrate improved performance compared with conventional capacitor materials.
It is one object of the present invention to provide a method of making a MIM capacitor which uses fewer process steps than conventional methods, thereby improving the time, cost, and complexity of the device manufacturing process.
It is another object of the present invention to achieve the first object by forming the capacitor and the wiring for the capacitor at the same time and on the same level of the device, thereby providing the dual advantage of reducing the time of manufacture and increasing integration density.
It is another object of the present invention to form the wiring using plate-through mask techniques, which techniques advantageously prevent the metal material used to form the conductive interconnects from falling into and thus contaminating the unfinished layers of the capacitor during simultaneousy capacitor formation.
It is another object of the present invention to achieve the first object by reducing the number of masking, etching, and polishing steps required to form the capacitor.
It is another object of the present invention to provide an MIM capacitor constructed from materials that demonstrate improved performance compared with conventional capacitors, which materials include conductive plates formed from copper which is cheaper, more efficient, and demonstrates a greater ability to hold a charge than metals used to for the conductive plates in conventional capacitors. Copper conductive plates also have lower sheet resistance and improved surface smoothness, both of which further contribute to improved performance of the capacitor.
It is another object of the present invention to provide an MIM capacitor with the aforementioned features formed from one of a single- or dual-damascene processes which advantageously further improves performance and integration density.
It is another object of the present invention to provide an MIM capacitor with the aforementioned features having an open-box shape.
The foregoing and other objects of the invention are achieved by providing a method which includes depositing a copper barrier and seed layer over support structure such as an inter-level dielectric layer, forming a dielectric over the copper barrier and seed layer, and then forming a forming a metal layer over the dielectric.
The copper barrier and seed layer forms a bottom plate of a capacitor, and the metal layer forms the upper plate which is separated from the bottom plate by the dielectric. By forming the bottom plate from a copper barrier and seed layer, the capacitor of the claimed invention achieves enhanced performance. This performance is only further enhanced by forming the capacitor to have a damascene structure.
In accordance with a preferred embodiment of the method of the present invention, at least one conductive interconnect is formed simultaneously with the capacitor. This is made possible by forming the interconnect in a via adjacent a trench in which the capacitor is formed. The copper barrier and seed layer is then deposited simultaneously in the trench and via. A photoresist is then placed in the trench and the via is electroplated with copper to form a stud that will form the interconnect. The resist is then removed and the dielectric and upper plate layers of the capacitor are deposited. This is followed by a planarizing step which ensures that top surfaces of the capacitor and stud (now an interconnect) are at an even level. Simultaneously forming the capacitor and interconnect in this manner reduces the time, cost, and complexity of the manufacturing process compared with conventional methods. The method also forms a capacitive structure having an open-box shape with increased integration density and improved capacitance.